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C8051T610/1/2/3/4/5/6/7
12. Comparator0 and Comparator1
C8051T610/1/2/3/4/5/6/7 devices include two on-chip programmable voltage comparators: Comparator0 is
shown in Figure 12.1, Comparator1 is shown in Figure 12.2. The two comparators operate identically with
the following exceptions: (1) Their input selections differ as described in Section “12.1. Comparator Multi-
plexers” on page 65; (2) Comparator0 can be used as a reset source.
The Comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 or CP1), or an
asynchronous “raw” output (CP0A or CP1A). The asynchronous signals are available even when the sys-
tem clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “21.4. Port I/O Initialization” on page 121). Comparator0 may also be used as a
reset source (see Section “19.5. Comparator0 Reset” on page 104).
The Comparator inputs are selected by the comparator input multiplexers, as detailed in Section
“12.1. Comparator Multiplexers” on page 65.
CPT0CN
VDD
CP0 +
Comparator
Input Mux
CP0 -
+
-
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
CP0
Crossbar
(SYNCHRONIZER)
CPT0MD
GND
Reset
Decision
Tree
CP0A
CP0RIF
0
1
CP0EN
0
EA
0
CP0
Interrupt
CP0FIF
0
1
1
1
Figure 12.1. Comparator0 Functional Block Diagram
58
Rev 1.1
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